Methodology

What we compute

The app answers one question: "how much water, electricity, and greenhouse gas is released to manufacture one chip of type X?"

The pipeline: per-process-step coefficients × step count → per-wafer totals ÷ good dies per wafer → per-die totals. We cover front-end-of-line and middle-of-line only — no packaging, no upstream mining, no use-phase energy.

Key assumptions

• Global-average grid intensity of 0.42 kg CO₂e/kWh used for Scope 2 emissions.
• Abatement (destruction/removal) efficiency for fluorinated gases assumed at ~95%.
• Yield values per chip based on published estimates where available, otherwise conservative defaults (70% baseline).
• 300mm wafer with 70,000 mm² usable area and 3 mm² scribe allowance per die.
• Water numbers show gross process water, not net withdrawal. TSMC recycles >95% internally — net would be 5-20× smaller.

Calibration

Coefficients were calibrated against three independent anchors:

• IMEC 2025: ~1,600 kg CO₂eq per wafer for a 2nm logic node.
• Hu 2023: ~5,750 L water per wafer (8.22 L/cm² × 700 cm²).
• Bardon 2020: N28→N2 scaling: 3.46× electricity, 2.3× water, 2.5× GHG.

All values are within ±18% of published anchors. Deltas are documented and transparent.

What these numbers are NOT

• Not suitable for regulatory reporting (CSRD, SEC, SB 253).
• Not suitable for carbon offset claims.
• Not a comparison between specific foundries or chipmakers.
• Not a full life-cycle assessment.

What they ARE

• Illustrative estimates for public education about orders of magnitude.
• A tool for comparing process nodes against each other.
• A reference for understanding which process families dominate which impact categories.

Sources

Acknowledgments

This tool relies on the pioneering sustainability work of IMEC's SSTS program, TSMC's ESG reporting, SEMI's sustainability publications, and the US EPA fluorinated gas partnership. The semiconductor industry has historically been opaque about environmental data — these organizations are changing that.